Program Counter Design

The Program Counter (PC) is a Presettable Synchronous 16bit Binary Counter made up from 4 * 74HC161 counters. 

Inputs 

• LPC_F_AB - H = Load PC from Address Bus i.e. Preset
• NOTIFZF - H = Don't load PC from Address Bus if Zero Flag is set (used in conjunction with LPC_F_AB to implement JNZ). 
• ZEROFLAG - Zero flag from Status Register
• MR_L - Master Reset (Low) - When low forces PC to reset to all zeros
•  EPC - Enable PC - L = Ouput PC onto Address Bus.

  Inputs/Outputs

• A[0..15] - Address Bus. 
  

Usage 

In normal use the PC outputs its value onto the Address Bus and then on the rising edge of the clock increments by 1.
- EPC = L (output PC onto address bus)
- LPC_F_AB = L (do not load PC from address bus)
- NOTIFZF = L
- ZEROFLAG = X
- MR_L = H (do not perform a master reset and reset PC to zero)

The PC can also be loaded from the value present on the Address Bus.
- EPC = H (do not output PC onto address bus)
- LPC_F_AB = H (load PC from address bus)
- NOTIFZF (set to H to not load if Zero Flag is set e.g. JNZ)
- MR_L = H (do not perform a master reset and reset PC to zero)

When Juno is reset (e.g. power on) then foce the PC to reset to zero by setting MR_L low. This resets the PC irrespective of the clock and other inputs.

Memory design

64kb memory providing 64k * 8 bit words

Based upon 2 * A56C2256 SRAM or similar and 1 * 74HCT138 demultiplexer.

Inputs

A0-15 -16 bit address bus
ME - memory enable. Active H disable L
OE - output enable. Active L disable H
WE - write enable. Active L disable H

Outputs/inputs

D0-7 - 8 bit data bus

The SRAM has a 15 bit address bus therefore the demux is used to enable the correct SRAM based upon the 16th bit of the address bus when ME is enabled.

The process for reading from memory is as follows.

1. Present the address on the address bus. Enable the memory by setting ME high. Enable output by setting OE high. Let the output settle and on clock latch data bus output.

The process for writing to memory is more complex as we need to be careful because the memory is not synchronous and will start writing to memory when WE and ME are enabled. If the address is not stable at that point in time it will start writing to whatever address(es) are presented on the address bus with disastrous results! This applies both when enabling and disabling i.e. we need to disable write before any operation which changes the address.

The process for writing to memory is as follows.

1. Present the address on the address bus and data on the databus. ME= L OE=H WE=H
2. Address now stable enable memory which will select the right chip by enabling the chip's CS. ME=H OE=H WE=H
3. Chip now selected enable write ME=H OE=H WE=L. The data on the databus will now be written to the address on the address bus.
4. disable write. ME=H OE=H WE=H. Ensure to keep address and data on buses valid.
5. Disable memory. ME=L OE=H WE=H. Keep address valid as according to the datasheet address changes should not happen when the chip is selected.

Default settings when not accessing memory are:
ME - L
OE - H
WE - H
To mask the microcode more intuitive it is tempting to flip the OE and WE around so L is disable.

Microcode Sequencer - Logical Design

First design for the microcode sequencer. The purpose of the sequencer is to run the micro-code program for the current instruction. Each line of the micro-code program sets the control lines that control the fundamental operation of the CPU.

The current instruction is loaded from the databus into the Instruction Register on the next clock signal (rising edge) by setting control line 1 to 'H'. For reasons that will become clear below only the 6 least significant bits (lsb) are used for the instruction meaning the Juno CPU instruction set can be up to 64 instructions. Hopefully, this is more than enough for a little accumulator CPU.

When a new instruction is loaded into the Instruction Register the Micro Program Counter must also be re-set to zero by setting control line 0 to 'H'.

Each instruction is implemented by a small micro-code program which is stored in the EEPROM. In order to determine the start address for the first line of the instruction's micro-code a simple trick is used. The EEPROM has a 10-bit address therefore the 6 bit Instruction Register forms the 6 most significant bits (msb) of the address and the 4 lsb are formed by the Micro Program Counter i.e. the first line of the micro-code is located at the address '<instruction code>0000'.

Using this approach each micro program can be up to 16 instructions in length. For example the first line of micro code for instruction code 0 is address 0; instruction code 1 starts at address 16; instruction code 2 starts at address 32 etc.  


The micro-code is then fetched from memory and sent to the de-multiplexer. As both the EEPROM and de-multiplexer are not synchronised to the clock the output will appear on the control lines immediately. The CPU's logic gates will then respond to the changed control lines and logic will "settle" to stable logic values, before the next clock signal occurs and the next micro-code is executed.

At the next clock signal the Micro Program Counter will increment by 1 and the next line of the micro program will be fetched from the memory. This will repeat until the last line of the micro-code program which will set control line 0 'H' to reset the Micro Program Counter and control line 1 'H' to load the next instruction into the Instruction Register.

The reset input allows the Micro Program Counter to be reset to zero when the CPU is re-set. 

Things to do

• Design the Program Counter (PC) circuitry and ensure the next instruction is ready on the databus

NB - I have re-numbered the control lines used by the ALU and will upload a revised design.

ALU - logical design

First design for the ALU. The ALU takes two 8-bit inputs 'A' and 'B' plus the Carry Flag 'C' and can perform 6 operations based upon how control inputs 1 to 6 are set.

Mathematical Operations

• Add
• Subtract

Subtraction relies on the fact that A + (-B) is the same A - B. B is converted to a negative number using 2s complement representation which requires all the bits to be inverted and then adding 1 by forcing the carry flag input to 1.

Logical Operations

• AND
• OR
• XOR
• NOT 

Outputs

• Result
• Zero flag - 1 if the output is equal to zero; 0 if the output is non-zero. The zero flag is set for every operation.
• Carry flag

The intention of the Zero Flag is to support Conditional Jump statements. It will be possible to implement compare instructions by not writing the Result to the Accumulator register.

The control lines are used as follows.

Control 1

• '0' select non-inverted 'B' into Adder (i.e. perform addition)
• '1' select inverted 'B' into Adder. (used to to perform subtraction)

Controls 2 and 3 

• '23'
• '00' select Carry Flag as input to Adder
• '10' force Carry Flag value to '1' as input into Adder (used to perform subtraction)
• '01' force Carry Flag value to '0' as input into Adder

Controls  4, 5 and 6 - select which operation to output as the result

• '456'
• '000' output the result of 'A' AND 'B'
• '100' output the result of 'A' OR 'B'
• '010' output the result of 'A' XOR 'B'
• '110' output the result of NOT 'B'
• '001' output the result of the Adder

NB Control lines 1 and 3 used to enable subtraction have been kept separate on the off chance it is useful to be able to control inversion and carry separately.