Memory design

64kb memory providing 64k * 8 bit words

Based upon 2 * A56C2256 SRAM or similar and 1 * 74HCT138 demultiplexer.

Inputs

A0-15 -16 bit address bus
ME - memory enable. Active H disable L
OE - output enable. Active L disable H
WE - write enable. Active L disable H

Outputs/inputs

D0-7 - 8 bit data bus

The SRAM has a 15 bit address bus therefore the demux is used to enable the correct SRAM based upon the 16th bit of the address bus when ME is enabled.

The process for reading from memory is as follows.

1. Present the address on the address bus. Enable the memory by setting ME high. Enable output by setting OE high. Let the output settle and on clock latch data bus output.

The process for writing to memory is more complex as we need to be careful because the memory is not synchronous and will start writing to memory when WE and ME are enabled. If the address is not stable at that point in time it will start writing to whatever address(es) are presented on the address bus with disastrous results! This applies both when enabling and disabling i.e. we need to disable write before any operation which changes the address.

The process for writing to memory is as follows.

1. Present the address on the address bus and data on the databus. ME= L OE=H WE=H
2. Address now stable enable memory which will select the right chip by enabling the chip's CS. ME=H OE=H WE=H
3. Chip now selected enable write ME=H OE=H WE=L. The data on the databus will now be written to the address on the address bus.
4. disable write. ME=H OE=H WE=H. Ensure to keep address and data on buses valid.
5. Disable memory. ME=L OE=H WE=H. Keep address valid as according to the datasheet address changes should not happen when the chip is selected.

Default settings when not accessing memory are:
ME - L
OE - H
WE - H
To mask the microcode more intuitive it is tempting to flip the OE and WE around so L is disable.